1. Field of the Invention
The present invention relates in general to power gating, and more particularly, to performing global voltage shift during power gating to momentarily increase the voltage of the gated supply bus to prevent the voltage of the gated supply bus from falling below a state retention voltage level in response to an impending change of a voltage of the global supply bus.
2. Description of the Related Art
Complementary MOS (CMOS) circuitry dissipates less power and is more dense than other types of integrated circuit (IC) technologies so that CMOS technology has become the dominant style of digital circuit design for integrated circuits. CMOS circuits use a combination of N-channel (NMOS) and P-channel (PMOS) devices or transistors each having a threshold gate-to-source voltage based on design, scale, materials and process. As IC design and fabrication techniques continue to evolve, operating voltages and device sizes have each scaled downward. As device sizes and voltage levels have decreased, the channel lengths and oxide thicknesses of each device have also decreased. Manufacturers have also switched to gate materials causing lower threshold voltages which has further led to increased sub-threshold leakage current. Sub-threshold leakage current is the current that flows between the drain and source when the gate-to-source voltage is below the threshold voltage of the CMOS device. In such conventional configurations the sub-threshold leakage current may account for nearly 15-30% or more of total power consumption in the dynamic environment (e.g., during normal operation).
For certain periods of time and/or under certain circumstances a CMOS circuit or a portion thereof may become idle in which it does not provide useful work. Maintaining full power to the idle circuit is wasteful and inefficient since sub-threshold leakage current continues to flow consuming valuable energy. For legacy CMOS technologies, the sub-threshold leakage current was reduced by adjusting the voltage of the bulk or body connections of the CMOS devices. This technique has not been as effective for current CMOS technologies at 40 nanometer (nm) and 28 nm and the like.